(I thought I posted this earlier, but it didn't appear so I am trying again)

Richard, et al

I have recently been addressing spurious interrupt issues on an LPC2000 processor. There are a variety of issues - related to the pipeline, the VIC, and some peripherals.

The issue I bring to this forum is one in the ARM core itself, due to the pipeline architecture. It involves a scenario in which an IRQ can happen with IRQ/FIQ interrupts disabled. This is discussed fairly well in the Philips User Manuals - I used UM10114_1.pdf.

My concern is with the point that if such an interrupt is processed without taking any special action, then FIQs remain disabled during the whole IRQ processing. There are several possible fixes, but for various reasons I like the one in which interrupts are disabled by first disabling IRQs, then disabling FIQs.

I have made this change in my version of FreeRTOS, but I suggest it should be in the distributed code. This would involve changing everywhere:

MRS    R0, CPSR ORR    R0, R0, #0xC0 MSR    CPSR, R0

to

MRS    R0, CPSR ORR    R0, R0, #0x80 MSR    CPSR, R0 ORR    R0, R0, #0x40 MSR    CPSR, R0

Glen

Thank you for your informative post.  I think your suggestion should be adopted.  Some ports use intrinsics to disable the interrupt __disable_interrupt() in IAR for example.  I think these should be changed to assembly also for consistency.

Some demo apps install a spurious interrupt handler and some dont.  Is there a reason for this?