FreeRTOS Support Archive
The FreeRTOS support forum is used to obtain active support directly from Real
Time Engineers Ltd. In return for using our top quality software and services for
free, we request you play fair and do your bit to help others too! Sign up
to receive notifications of new support topics then help where you can.
This is a read only archive of threads posted to the FreeRTOS support forum.
The archive is updated every week, so will not always contain the very latest posts.
Use these archive pages to search previous posts. Use the Live FreeRTOS Forum
link to reply to a post, or start a new support thread.
[FreeRTOS Home] [Live FreeRTOS Forum] [FAQ] [Archive Top] [March 2017 Threads] FreeRTOS Sharing Memory between coresPosted by iamshut on March 16, 2017 I have some probles with memory reads operations in multiple core platforms. I have a dual-core with a Cortex-A9 with U-Boot and a Cortex-M4with FreeRTOS. From the FreeRTOS I read data pointing to the physical address of the memory:
volatile char readAddressData;
volatile char *writeAddressData = (char *) 0x91F000;
readAddressData = *writeAddressData;
The data read is checked with U-Boot doing:
md 91f000
However, if the data of the memory is modified (mw 91f000 aaaaaaaa), the changes are not read in the FreeRTOS. Do somebody know why?
Thank you
FreeRTOS Sharing Memory between coresPosted by rtel on March 16, 2017 If the memory is written by one core and read by another you will
probably need to perform a cache flush after the write before it becomes
visible to the reader.
FreeRTOS Sharing Memory between coresPosted by iamshut on March 17, 2017 I do a "dchache flush" after writing in U-Boot. HOwever, the core reading does not detect the changes.
FreeRTOS Sharing Memory between coresPosted by rtel on March 17, 2017 As a hardware question this really falls outside of FreeRTOS support. I
would recommend describing the issue to the hardware manufacturer and
see what they recommend.
FreeRTOS Sharing Memory between coresPosted by heinbali01 on March 17, 2017 Although this subject is a bit off-topic for FreeRTOS, I'll give my two cents:
● Are you sure that there is no memory-address translation within uboot? If you write to address 0x91F000, is that really the first byte of the shared memory?
● Are you sure that the mapping for that physical memory within the Cortex-M4 is the same? Also at address 0x91F000?
● is memory access from within the Cortex-M4 without caching? If not a refresh would be necessary
● and last of all: wouldn't it be possible to reserve a block of uncached shared memory for this purpose?
Copyright (C) Amazon Web Services, Inc. or its affiliates. All rights reserved.
|