I am so disappointed. I just 30mins typing up this yesterday and SourceForge "had an error" when I tried to post it - so it's all gone :-( I should have learnt by now to copy things to the clipboard before submitting...

I'm trying to work out if there is a problem with my understanding or with the IAR Cortex M3 port.c file.

I've just upgraded to FreeRTOS 7.5.0 and enabled the configASSERT() macro. It showed that I had a few problems.

I fixed the first one in vPortValidateInterruptPriority( ) by making sure that I called NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); before calling NVIC_Init(&NVIC_InitStructure);. If you dig deep into the STM32 Standard Peripheral library docs it does say to do this but I didn't notice. If you don't do this then NVIC_Init sets the interrupt priority to zero - causing configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); to fail.

But I got stuck on this one:

/* Priority grouping:  The interrupt controller (NVIC) allows the bits
that define each interrupt's priority to be split between bits that
define the interrupt's pre-emption priority bits and bits that define
the interrupt's sub-priority.  For simplicity all bits must be defined
to be pre-emption priority bits.  The following assertion will fail if
this is not the case (if some bits represent a sub-priority). 

If CMSIS libraries are being used then the correct setting can be
achieved by calling    NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0x0000 );

After I call NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); the priority bits in AIRCR are set to 3, not zero. To get things to work I had to change the assertion to

configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0x0300 );

Is that a bug in the port.c file? It seems to work ok once I've changed it.

I find it still has hard-aborts in ISR's but I'll do some more reading before asking for help.

Peter
PS Some of the info is here to help someone else who comes across the same problem

PS the comment just above the assert for priorities says

If CMSIS libraries are being used then the correct setting can be achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler

This is the opposite of what it says on the Cortex M3/M4 page here,where it says
Most systems default to the wanted configuration, with the noticeable exception of the STM32 driver library. If you are using an STM32 with the STM32 driver library then ensure all the priority bits are assigned to be preempt priority bits by calling NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); before the RTOS is started

This is an issue specific to users of the STM32 peripheral library because the library makes assumptions about the Cortex registers which means you cannot use a default chip configuration. Read the very top entry in the revision history http://www.freertos.org/History.txt for your answer.

I would also recommend adding yourself to the mailing list, or better still the new twitter feed. You will find links to both on the FreeRTOS website.

Regards.

Thanks Richard. I hadn't noticed there was a new version - perhaps the header at the top of the website which announces 7.5.0 could be updated?
I've added myself to the mailing list for next time.

regards